1. Technical Field
Various embodiments relate to a semiconductor integrated circuit, and more particularly, to a semiconductor memory apparatus.
2. Related Art
In general, a semiconductor memory apparatus is configured to store data and output the stored data. The semiconductor memory apparatus includes a memory cell which stores data, a bit line which transfers the voltage stored in the memory cell to a sense amplifier, and the sense amplifier which senses and amplifies the voltage applied from the bit line.
Referring to FIG. 1, a conventional semiconductor memory apparatus includes a sense amplifier driving unit 10 and a sense amplifier 20.
The sense amplifier driving unit 10 applies first and second sense amplifier driving voltages VDD and VSS to first and second sense amplifier driving nodes RTO and SB, respectively, in response to first to third sense amplifier driving signals SAP, SAN and SAPCG. For example, the sense amplifier driving unit 10 applies the first sense amplifier driving voltage VDD to the first sense amplifier driving node RTO when the first sense amplifier driving signal SAP is enabled with the third sense amplifier driving signal SAPCG disabled. Also, the sense amplifier driving unit 10 applies the second sense amplifier driving voltage VSS to the second sense amplifier driving node SB when the second sense amplifier driving signal SAN is enabled with the third sense amplifier driving signal SAPCG disabled. When the third sense amplifier driving signal SAPCG is enabled, the sense amplifier driving unit 10 couples the first and second sense amplifier driving nodes RTO and SB and applies a bit line precharge voltage VBLP to the coupled nodes RTO and SB.
The sense amplifier driving unit 10 includes first to fifth transistors N1 to N5. The first transistor N1 has a gate which receives the first sense amplifier driving signal SAP, a drain which is applied with an external voltage VDD, and a source to which the first sense amplifier driving node RTO is coupled. In the case where the first transistor N1 is turned on by the first sense amplifier driving signal SAP, the external voltage VDD is outputted as the first sense amplifier driving voltage VDD to the first sense amplifier driving node RTO. The second transistor N2 has a gate which receives the third sense amplifier driving signal SAPCG, a drain to which the first sense amplifier driving node RTO is coupled, and a source to which the second sense amplifier driving node SB is coupled. The third transistor N3 has a gate which receives the third sense amplifier driving signal SAPCG, a drain which is applied with the bit line precharge voltage VBLP, and a source to which the first sense amplifier driving node RTO is coupled. The fourth transistor N4 has a gate which receives the third sense amplifier driving signal SAPCG, a drain which is applied with the bit line precharge voltage VBLP, and a source to which the second sense amplifier driving node SB is coupled. The drains of the third transistor N3 and the fourth transistor N4 are commonly coupled to each other, and a node to which the drains of the third transistor N3 and the fourth transistor N4 are commonly coupled is applied with the bit line precharge voltage VBLP. The fifth transistor N5 has a gate which receives the second sense amplifier driving signal SAN, a drain to which the second sense amplifier driving node SB is coupled, and a source which is applied with a ground voltage VSS. When the second sense amplifier driving signal SAN is enabled, the fifth transistor N5 outputs the ground voltage VSS as the second sense amplifier driving voltage VSS to the second sense amplifier driving node SB.
The sense amplifier 20 senses and amplifies the voltage level difference of a bit line BL and a bit line bar BLb when the first and second sense amplifier driving voltages VDD and VSS are applied to the first and second sense amplifier driving nodes RTO and SB.
In the semiconductor memory apparatus configured as mentioned above, in the case where the external voltage VDD is initially applied to the semiconductor memory apparatus, a case is likely to occur in which the voltage levels of the first to third sense amplifier driving signals SAP, SAN and SAPCG are not initialized. If all of the first to third sense amplifier driving signals SAP, SAN and SAPCG are not initialized, all of the first transistor N1, the second transistor N2 and the fifth transistor N5 may be turned on. Consequently, as current paths are formed through the first and second transistors N1 and N2 and the fifth transistor N5 turned on in this way, current may be unexpectedly consumed.